The present embodiments relate to microprocessor systems, and are more particularly directed to microprocessor circuits, systems, and methods for conditioning information prefetching based on a resource burden of the system.
The present embodiments relate to the ever-expanding field of computer systems, and may apply in various instances to both single and multiple microprocessor-based systems. As all of these types of systems advance, designers strive to increase performance while minimizing costs. Indeed, significant advances have been made in the design of microprocessors to improve their performance, as measured by the number of operations performed over a given time period.
One advancement in microprocessor operation relates to the concept of prefetching information. Prefetched information may be either data or instructions. As is known in the art, a block of information is often prefetched from some storage device which is at a relatively high order in the memory hierarchy, such as a memory which is external from the integrated circuit which includes the microprocessor. In a multiple microprocessor system, a common external memory may be accessed by prefetches performed by each microprocessor in the system. In any event, once information is prefetched, it is commonly written to a storage device lower in the storage hierarchy, such as in a lower order cache or the like. Prefetching in either of the above manners provides the benefit of allowing the time spent to retrieve such information to occur concurrent with other actions of the microprocessor so that once the prefetched information is actually used by the microprocessor there is either a reduced or no delay in then having to fetch the information; thus, prefetching reduces or eliminates some of the cache miss penalty by having such a miss occur during other processing.
The event triggering prefetching is often some type of speculative activity which suggests that the information is likely to be needed for subsequent operations. Numerous types of prefetching are known in the art. Without an exhaustive listing, however, some examples are illustrative. One type of prefetching often occurs where an instruction fetch unit in an instruction pipeline fetches a group of instructions. Particularly, the instruction fetch unit may perform a prefetch in response to an indication in a branch target buffer or the like. In this instance, the branch target buffer predicts (i.e., speculates) that an information unit at a branch target address will be needed by the microprocessor and, therefore, this speculative information unit is prefetched. Another type of prefetching often occurs where an instruction fetch unit in an instruction pipeline prefetches blocks of data in response to a load target buffer. As known in the art, a load target buffer predicts loads and stores based on past data cache misses. Therefore, it is beneficial to prefetch one or more information units which may not already be in the cache as predicted in this manner. Still another type of prefetching occurs for certain instructions, such as those involved with certain block or string-related operations. Specifically, for such operations, it is often known that the string at issue will include numerous words (or some other quantity such as a double-word), yet the microprocessor may be able to handle only one word (or other quantity) at a time. In this instance, the microprocessor will initially fetch the first word of the string, yet will concurrently commence a prefetch of some or all of the remaining words of the string so that those remaining words are more readily accessible for processing after the first word is fetched. Still other examples of operations which induce a prefetch operation are also known in the art so that, while the system is processing an instruction, separate circuitry concurrently prefetches a block of information with the expectation that such information will be needed by operations following the current instruction. Consequently, if indeed additional instructions then require the prefetched information, it is accessible from the lower order storage device rather than having to then retrieve it from a higher level storage device and incurring the potentially large number of clock cycles needed to perform such a retrieval.
While prefetching according to the manners above as well as known in the art may therefore improve performance, the present inventors have recognized various drawbacks resulting from such techniques. Thus, below is provided a discussion of some of such drawbacks as well as various embodiments which reduce the effects of such drawbacks and, therefore, improve upon the prior art.
In a computer system embodiment, there is included a memory and circuitry for prefetching information from the memory in response to a prefetch request. The system further includes a system resource, wherein the system resource is burdened in response to a prefetch operation by the circuitry for prefetching information. The system resource is also further burdened in response to other circuitry using the system resource. The system further includes circuitry for determining a measure of the burden on the system resource. Lastly, the system includes circuitry for prohibiting prefetching of the information by the circuitry for prefetching information in response to a comparison of the measure of the burden with a threshold. Other circuits, systems, and methods are also disclosed and claimed.